The present invention relates to a prescaler and, more particularly, to a buffer for a prescaler.
In recent years, communication terminal devices, such as cellular phones, have become widely used, and various communication formats exist in the field of wireless communication. Each communication format uses a different frequency band. Thus, a base station is required to have a PLL frequency synthesizer that operates in a broad band and is capable of receiving radio waves in a broad frequency band. Accordingly, it is also required that the PLL frequency synthesizer use a prescaler and a buffer circuit that is operable in a broad band.
In the prior art, a PLL frequency synthesizer is used to stably obtain frequencies corresponding to many channels. The PLL frequency synthesizer locks a phase by using the output of a crystal oscillator and obtains the desired frequency by adjusting a frequency dividing ratio. In such a PLL frequency synthesizer, a prescaler for reducing the frequency is used.
FIG. 1 is a schematic circuit diagram showing a prescaler 10 in the prior art.
The prescaler 10 includes a buffer 11 and a counter 12. The buffer 11 includes a plurality of series-connected inverter circuits 13a, 13b, 13c, 13d, and 13e. The first inverter circuit 13a has an input terminal connected to a capacitor (not shown). Thus, a feedback resistor R1, which applies self-bias on the inverter circuit 13a, is connected between the input and output terminals of the inverter circuit 13a. 
Japanese Laid-Open Patent Publication No. 6-197011 describes a prescaler that operates in a broad band. Further, Japanese Laid-Open Patent Publication No. 9-261012 describes a buffer circuit for a voltage controlled oscillator having a linear voltage-frequency characteristic.